1. Field of the Invention
The present invention relates to an insulated gate field effect transistor of a self-aligned structure which uses a thin film layer made of amorphous silicon, microcyrstalline silicon or polycrystalline silicon, etc., and more particularly, to a structure of the above thin film transistor (hereinafter referred to as a TFT) and a method for making the same which can greatly simplify the process thereof and highly maintain the pattern accuracy of source drain electrodes with respect to a gate electrode.
2. Description of the Prior Art
Generally, as shown in FIG. 1, a thin film transistor (TFT) using amorphous silicon (hereinafter referred to as a-Si) is constructed in such a manner that after a gate electrode 2 is formed on an insulating substrate 1 made of glass or the like, an insulator film 3 is coated thereon. Then, an a-Si layer 4 is deposited on the insulator film 3. Thereafter, a source electrode 5 and a drain electrode 6 are formed such that their edge portions partly overlap and contact with the a-Si layer 4. For the gate electrode 2, metal such as Al, Ni-Cr or Mo is employed. For the gate insulator film 3, SiO.sub.2 film or Si.sub.3 N.sub.4 film which is obtained by, for example, a chemical vapor deposition method (CVD method) or by a plasma CVD method is employed. Generally, the a-Si layer 4 is deposited onto the gate insulator film 3 by glow-discharge decomposition of SiH.sub.4. In addition, both the source electrode 5 and drain electrode 6 may also be formed by an n+a-Si film etc.
When the thin film transistor (TFT) of the above described type is used in an address element in a matrix-type liquid crystal display device, it is necessary to align the pattern of the semiconductor layer and the source drain electrodes with a predetermined gate pattern over a wide area with a very high precision, such as in the order of less than several micrometers. Thus, the positioning of such electrodes also must be done with a very high accuracy.
An improvement has been made to the above-described TFT. That is, a thin film transistor (TFT) of a self-aligned structure which requires no alignment of the source and drain electrodes with respect to the gate electrode, because the positioning of the respective electrodes are automatically determined. A method for making the self-aligned TFT is disclosed, for example, in IEEE, Electron Device Letters Vol. EDL-3, No. 7 July 1982 by T. Kodama et al. According to this article, as illustrated in FIGS. 2 through 5, the self-alignment method makes use of a positive photoresist in order to determine the positions of the source and drain electrodes. In other words, after gate electrode 2, insulator film 3 and a-Si layer 4 are consecutively deposited on glass substrate 1 as shown in FIG. 2, a positive photoresist is laminated on a-Si layer 4 and, thereafter the light is irradiated from a bottom face of glass substrate 1. When the light is irradiated, gate electrode 2 shields the light rays and prevents the photoresist thereon from being exposed. Accordingly, a positive photoresist pattern 7, which has the same configuration as that of the gate electrode 2, is formed as shown in FIG. 3. Then, Al-film is deposited on the photoresist pattern 7 and a-Si layer 4. Then, when the photoresist pattern 7 is removed together with Al-film deposited thereon through a lift-off method, source electrode 5 and drain electrode 6 are formed, as shown in FIG. 4. This process is called a self-alignment process.
According to the above method, it is necessary to further provide an etching process for determining the width of the channel so as to provide a complete TFT. Morevoer, in order to enable the exposure process from the bottom of glass substrate 1, it is necessary to form source and drain electrodes through the self-alignment process on thin a-Si layer 4, which has the thickness of less than 200.ANG.. Furthermore in order to produce a FET which can perform favorably, it is necessary to form a thick a-Si layer 41, which has the thickness over several thousand .ANG. deposited thereon, as shown in FIG. 5, and thereafter, the deposited a-Si layer 41 should be covered with an insulator film 8 thereby obtaining favorable performance.
Therefore, according to the prior art process for making the TFT, the process itself is very complicated. Furthermore, the layers formed on the top surface of the glass substrate may easily be soiled or spoiled during the exposure process of light from the bottom face of the substrate. Moreover, in the case where the source and drain electrodes are formed by, e.g., Al, an etchant, such as HF, cannot be used to form patterns of the thick a-Si layer 41. Instead, the thick a-Si layer 41 should be patterned by dryetching by the use of CF.sub.4. Thus, from practical viewpoint, the self-alignment process disclosed in the aforementioned article is not suitable for forming a thin film transistor array for use in a matrix-type liquid crystal display device.